Ternary content-addressable memories (TCAMs) are used to design high-speed search\nengines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and\nfield-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs)\nplatforms but both have the drawback of high power consumption. This paper presents a\npre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification\nstage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based\nimplementation stage maps each of the resultant TCAM sub-tables to a separate row of configured\nSRAM blocks in the architecture. The proposed architecture selectively activates at most one row\nof SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM\ndesigns on FPGAs, the proposed design consumes significantly reduced energy as it activates a part\nof SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes.\nWe implemented the proposed approach sample designs of size 512 Ã? 36 on Xilinx Virtex-6 FPGA.\nThe experimental results showed that the proposed design achieved at least three times lower power\nconsumption per performance than other SRAM-based TCAM architectures.
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